Commit 020a4257 authored by E. Bruin de's avatar E. Bruin de
Browse files

- add missing files

parent 90662f8e
##################################
## MUST BE SOURCED AS LEGACY !! ##
##################################
set_db common_ui false
set clk iClk
set rst iReset
set func_clk [find /designs -pin $DESIGN/*/$clk]
if {$DESIGN=="CGRA_Core" || $DESIGN=="CGRA_Compute_Wrapper" || $DESIGN=="CGRA_Top" } {
#can be changed if timing violations occur, but only do so after coordinating
set SWB_DELAY 0.2
set FU_OUT_DELAY 1.0
set FU_DELAY 2.4
set LSU_DELAY 2.0
set FU_BUF_DELAY 0.40
#finds all buffer pins, make sure (we could do this together once) that everything
#gets found.
set buffers_in [find / -pin */*CGRA_Compute*/*/*buffer_swb*/*bitbuf*/I]
set buffers_out [find / -pin */*CGRA_Compute*/*/*buffer_swb*/*bitbuf*/Z]
set fu_buffers_in [find / -pin */*CGRA_Compute*/*/*buffer_FU*/*bitbuf*/I]
set fu_buffers_out [find / -pin */*CGRA_Compute*/*/*buffer_FU*/*bitbuf*/Z]
set lsu_buffers_in [find / -pin */*CGRA_Compute*/*/*buffer_lsu*/*bitbuf*/I]
set lsu_buffers_out [find / -pin */*CGRA_Compute*/*/*buffer_lsu*/*bitbuf*/Z]
set alu_buffers_in [find / -pin */*CGRA_Compute*/*/*buffer_alu*/*bitbuf*/I]
set alu_buffers_out [find / -pin */*CGRA_Compute*/*/*buffer_alu*/*bitbuf*/Z]
set buffers [find / -instance */*CGRA_Compute*/*/*/*bitbuf*]
set buffer_cells [dc::get_cell $buffers]
#preserve buffer pins
if {$buffers_in!=""} {set_attribute preserve true $buffers_in}
if {$buffers_out!=""} {set_attribute preserve true $buffers_out}
if {$fu_buffers_in!=""} {set_attribute preserve true $fu_buffers_in}
if {$fu_buffers_out!=""} {set_attribute preserve true $fu_buffers_out}
if {$lsu_buffers_in!=""} {set_attribute preserve true $lsu_buffers_in}
if {$lsu_buffers_out!=""} {set_attribute preserve true $lsu_buffers_out}
if {$alu_buffers_in!=""} {set_attribute preserve true $alu_buffers_in}
if {$alu_buffers_out!=""} {set_attribute preserve true $alu_buffers_out}
#disable timing arc through buffers
if {$buffer_cells!=""} {dc::set_disable_timing $buffer_cells}
#specify the propagation times, these should not be marked as ignored after running
#report timing -lint -verbose !!!!!
if {$buffers_out!="" && $fu_buffers_in!=""} {dc::set_max_delay -exception_name lb_fu -from $buffers_out -to $fu_buffers_in $SWB_DELAY}
if {$buffers_out!="" && $buffers_in!=""} {dc::set_max_delay -exception_name lb_lb -from $buffers_out -to $buffers_in $SWB_DELAY}
if {$buffers_in!=""} {dc::set_max_delay -exception_name ff_lb -from $func_clk -to $buffers_in $FU_OUT_DELAY}
if {$fu_buffers_in!=""} {dc::set_max_delay -exception_name ff_fu -from $func_clk -to $fu_buffers_in $FU_OUT_DELAY}
if {$lsu_buffers_out!="" && $buffers_in!=""} {dc::set_max_delay -exception_name lsu_lb -from $lsu_buffers_out -to $buffers_in $FU_BUF_DELAY}
if {$lsu_buffers_out!="" && $fu_buffers_in!=""} {dc::set_max_delay -exception_name lsu_fu -from $lsu_buffers_out -to $fu_buffers_in $FU_BUF_DELAY}
if {$alu_buffers_out!="" && $buffers_in!=""} {dc::set_max_delay -exception_name alu_lb -from $alu_buffers_out -to $buffers_in $FU_BUF_DELAY}
if {$alu_buffers_out!="" && $fu_buffers_in!=""} {dc::set_max_delay -exception_name alu_fu -from $alu_buffers_out -to $fu_buffers_in $FU_BUF_DELAY}
#fu delays
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_ff -from $fu_buffers_out -to $func_clk $FU_DELAY}
if {$fu_buffers_out!="" && $alu_buffers_in!=""} {dc::set_max_delay -exception_name fu_alu -from $fu_buffers_out -to $alu_buffers_in $FU_DELAY}
if {$lsu_buffers_in!=""} {dc::set_max_delay -exception_name mem_lsu -from $func_clk -to $lsu_buffers_in $LSU_DELAY}
#some paths in the CGRA ended up over-constrained, these get more relaxed constraints here
set dtl_seq [find / * *CGRA_Compute_Wrapper*/*/DTL_DMEM_MASTER_inst/instances_seq/*]
set seq_arb [find / * */*CGRA_Compute*/*/*/*/*/*arb_inst*/instances_seq*/r*]
set seq_lsu [find / * */*CGRA_Compute*/*/instances_seq*/*Wait*]
set seq_loader [find / * */*CGRA_Compute*/*LOADER*/instances_seq*/*]
set seq_wrapper [find / * */*CGRA_Compute*/*/rCGRA_Reset_reg]
set seq_config [find / * */*CGRA_Compute*/*/*SWB_*/*instances_seq*/*rConfig*]
#check if it is the DTL or native memory interface
if {$dtl_seq==""} {set mem_int "NATIVE"} else {set mem_int "DTL"}
if {$mem_int=="DTL"} {
dc::set_max_delay -exception_name loader_dtl -from $seq_loader -to $dtl_seq 3.0
dc::set_max_delay -exception_name lsu_dtl -from $lsu_buffers_out -to $dtl_seq 3.0
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_dtl -from $fu_buffers_out -to $dtl_seq 3.0}
} else {
if {$fu_buffers_out!=""} {
set stall_signals [find / -pin *Stall*]
set arb_pins [find / -pin */*ARBITER*/*Arb*]
set output_ports [find / -port o*]
#2.6 5.0
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name stallsignals_abu -from $fu_buffers_out -through $stall_signals -to $func_clk 5.0}
#2.6 4.3
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name arbiter_signals -from $fu_buffers_out -through $arb_pins -to $func_clk 5.0} #5
#4.0
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_output -from $fu_buffers_out -to $output_ports 5.0} #5
}
}
if {$fu_buffers_out!="" && $seq_arb!=""} {dc::set_max_delay -exception_name fu_arb -from $fu_buffers_out -to $seq_arb 3.0}
if {$fu_buffers_out!="" && $seq_lsu!=""} {dc::set_max_delay -exception_name fu_lsu -from $fu_buffers_out -to $seq_lsu 3.0}
if {$buffers_in!="" && $seq_loader!=""} {dc::set_max_delay -exception_name loader_lb -from $seq_loader -to $buffers_in 3.0}
if {$fu_buffers_in!="" && $seq_loader!=""} {dc::set_max_delay -exception_name loader_fu -from $seq_loader -to $fu_buffers_in 3.0}
if {$buffers_in!="" && $seq_wrapper!=""} {dc::set_max_delay -exception_name wrapper_lb -from $seq_wrapper -to $buffers_in 3.0}
if {$fu_buffers_in!="" && $seq_wrapper!=""} {dc::set_max_delay -exception_name wrapper_fu -from $seq_wrapper -to $fu_buffers_in 3.0}
if {$buffers_in!="" && $seq_config!=""} {dc::set_max_delay -exception_name config_lb -from $seq_config -to $buffers_in 3.0}
if {$fu_buffers_in!="" && $seq_config!=""} {dc::set_max_delay -exception_name config_fu -from $seq_config -to $fu_buffers_in 3.0}
#for some (unknown) reason the DTL interface does not work if clock gated, clock gating
# is disabled for DTL interfaces within the CGRA
# OLD: set_attribute lp_clock_gating_exclude true */*CGRA_Compute_Wrapper*/*instances_hier*/*DTL*
#set_attribute lp_clock_gating_exclude true [find . -instance */*CGRA_Compute_Wrapper*/*instances_hier*/*DTL*]
#set_attribute lp_clock_gating_exclude true [find . -instance */*CGRA_Compute_Wrapper*/*instances_hier*/*LOADER*]
#set_attribute lp_clock_gating_exclude true [find . -instance */*CGRA_Compute_Wrapper*/*instances_hier*/*CGRA_Compute*/*instances_hier*/*lsu*]
set gm_out [find / -pin */CGRA_Top/GM_inst/genblk1.mem_inst/*]
#4.0
if {$fu_buffers_out!="" && $gm_out!=""} {dc::set_max_delay -exception_name fu_gm -from $fu_buffers_out -to $gm_out 2.8}
#if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_ff -from $fu_buffers_out -to $func_clk $FU_DELAY}
#reset input is asynchronous and therefore should be a false path
dc::set_false_path -from */$DESIGN/ports_in/iReset -exception_name reset
}
set_attribute common_ui true
##################################
## MUST BE SOURCED AS LEGACY !! ##
##################################
##### CGRA timing constraints ##############
#can be changed if timing violations occur, but only do so after coordinating
#set_db common_ui false
set SWB_DELAY 0.2
set FU_OUT_DELAY 1.0
set FU_DELAY 2.4
set LSU_DELAY 2.0
set FU_BUF_DELAY 0.40
#finds all buffer pins, make sure (we could do this together once) that everything
#gets found.
set CGRACI CGRA_Top/CGRA_Core_inst/CGRA_Compute_Wrapper_inst/CGRA_Compute_inst
if {[catch {set buffers_in [vfind $CGRACI/*/buffer_swb*/*bitbuf* -pin I]}]} {puts "NO SWB buf in"; set buffers_in ""}
if {[catch {set buffers_out [vfind $CGRACI/*/buffer_swb*/*bitbuf* -pin Z]}]} {puts "NO SWB buf out"; set buffers_out ""}
if {[catch {set fu_buffers_in [vfind $CGRACI/*/buffer_FU*/*bitbuf* -pin I]}]} {puts "NO FU buf in"; set fu_buffers_in ""}
if {[catch {set fu_buffers_out [vfind $CGRACI/*/buffer_FU*/*bitbuf* -pin Z]}]} {puts "NO FU buf out"; set fu_buffers_out ""}
if {[catch {set lsu_buffers_in [vfind $CGRACI/*/buffer_lsu*/*bitbuf* -pin I]}]} {puts "NO LSU buf in"; set lsu_buffers_in ""}
if {[catch {set lsu_buffers_out [vfind $CGRACI/*/buffer_lsu*/*bitbuf* -pin Z]}]} {puts "NO LSU buf out"; set lsu_buffers_out ""}
if {[catch {set alu_buffers_in [vfind $CGRACI/*/buffer_alu*/*bitbuf* -pin I]}]} {puts "NO ALU buf in"; set alu_buffers_in ""}
if {[catch {set alu_buffers_out [vfind $CGRACI/*/buffer_alu*/*bitbuf* -pin Z]}]} {puts "NO ALU buf out"; set alu_buffers_out ""}
set buffer_cells [vfind $CGRACI/*/*/*bitbuf*]
#preserve buffer pins
if {$buffers_in!=""} {set_db inst:$buffers_in .preserve true}
if {$buffers_out!=""} {set_db inst:$buffers_out .preserve true}
if {$fu_buffers_in!=""} {set_db inst:$fu_buffers_in .preserve true}
if {$fu_buffers_out!=""} {set_db inst:$fu_buffers_out .preserve true}
if {$lsu_buffers_in!=""} {set_db inst:$lsu_buffers_in .preserve true}
if {$lsu_buffers_out!=""} {set_db inst:$lsu_buffers_out .preserve true}
if {$alu_buffers_in!=""} {set_db inst:$alu_buffers_in .preserve true}
if {$alu_buffers_out!=""} {set_db inst:$alu_buffers_out .preserve true}
#disable timing arc through buffers
#if {$buffer_cells!=""} {dc::set_disable_timing $buffer_cells}
#specify the propagation times, these should not be marked as ignored after running
#report timing -lint -verbose !!!!!
if {$buffers_out!="" && $fu_buffers_in!=""} {dc::set_max_delay -exception_name lb_fu -from $buffers_out -to $fu_buffers_in $SWB_DELAY}
if {$buffers_out!="" && $buffers_in!=""} {dc::set_max_delay -exception_name lb_lb -from $buffers_out -to $buffers_in $SWB_DELAY}
if {$buffers_in!=""} {dc::set_max_delay -exception_name ff_lb -from $func_clk -to $buffers_in $FU_OUT_DELAY}
if {$fu_buffers_in!=""} {dc::set_max_delay -exception_name ff_fu -from $func_clk -to $fu_buffers_in $FU_OUT_DELAY}
if {$lsu_buffers_out!="" && $buffers_in!=""} {dc::set_max_delay -exception_name lsu_lb -from $lsu_buffers_out -to $buffers_in $FU_BUF_DELAY}
if {$lsu_buffers_out!="" && $fu_buffers_in!=""} {dc::set_max_delay -exception_name lsu_fu -from $lsu_buffers_out -to $fu_buffers_in $FU_BUF_DELAY}
if {$alu_buffers_out!="" && $buffers_in!=""} {dc::set_max_delay -exception_name alu_lb -from $alu_buffers_out -to $buffers_in $FU_BUF_DELAY}
if {$alu_buffers_out!="" && $fu_buffers_in!=""} {dc::set_max_delay -exception_name alu_fu -from $alu_buffers_out -to $fu_buffers_in $FU_BUF_DELAY}
#fu delays
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_ff -from $fu_buffers_out -to $func_clk $FU_DELAY}
if {$fu_buffers_out!="" && $alu_buffers_in!=""} {dc::set_max_delay -exception_name fu_alu -from $fu_buffers_out -to $alu_buffers_in $FU_DELAY}
if {$lsu_buffers_in!=""} {dc::set_max_delay -exception_name mem_lsu -from $func_clk -to $lsu_buffers_in $LSU_DELAY}
#some paths in the CGRA ended up over-constrained, these get more relaxed constraints here
set dtl_seq [find / * *CGRA_Compute_Wrapper*/*/DTL_DMEM_MASTER_inst/instances_seq/*]
set seq_arb [find / * */*CGRA_Compute*/*/*/*/*/*arb_inst*/instances_seq*/r*]
set seq_lsu [find / * */*CGRA_Compute*/*/instances_seq*/*Wait*]
set seq_loader [find / * */*CGRA_Compute*/*LOADER*/instances_seq*/*]
set seq_wrapper [find / * */*CGRA_Compute*/*/rCGRA_Reset_reg]
set seq_config [find / * */*CGRA_Compute*/*/*SWB_*/*instances_seq*/*rConfig*]
#check if it is the DTL or native memory interface
if {$dtl_seq==""} {set mem_int "NATIVE"} else {set mem_int "DTL"}
if {$mem_int=="DTL"} {
dc::set_max_delay -exception_name loader_dtl -from $seq_loader -to $dtl_seq 3.0
dc::set_max_delay -exception_name lsu_dtl -from $lsu_buffers_out -to $dtl_seq 3.0
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_dtl -from $fu_buffers_out -to $dtl_seq 3.0}
} else {
if {$fu_buffers_out!=""} {
set stall_signals [find / -pin *Stall*]
set arb_pins [find / -pin */*ARBITER*/*Arb*]
set output_ports [find / -port o*]
#2.6 5.0
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name stallsignals_abu -from $fu_buffers_out -through $stall_signals -to $func_clk 5.0}
#2.6 4.3
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name arbiter_signals -from $fu_buffers_out -through $arb_pins -to $func_clk 5.0} #5
#4.0
if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_output -from $fu_buffers_out -to $output_ports 5.0} #5
}
}
if {$fu_buffers_out!="" && $seq_arb!=""} {dc::set_max_delay -exception_name fu_arb -from $fu_buffers_out -to $seq_arb 3.0}
if {$fu_buffers_out!="" && $seq_lsu!=""} {dc::set_max_delay -exception_name fu_lsu -from $fu_buffers_out -to $seq_lsu 3.0}
if {$buffers_in!="" && $seq_loader!=""} {dc::set_max_delay -exception_name loader_lb -from $seq_loader -to $buffers_in 3.0}
if {$fu_buffers_in!="" && $seq_loader!=""} {dc::set_max_delay -exception_name loader_fu -from $seq_loader -to $fu_buffers_in 3.0}
if {$buffers_in!="" && $seq_wrapper!=""} {dc::set_max_delay -exception_name wrapper_lb -from $seq_wrapper -to $buffers_in 3.0}
if {$fu_buffers_in!="" && $seq_wrapper!=""} {dc::set_max_delay -exception_name wrapper_fu -from $seq_wrapper -to $fu_buffers_in 3.0}
if {$buffers_in!="" && $seq_config!=""} {dc::set_max_delay -exception_name config_lb -from $seq_config -to $buffers_in 3.0}
if {$fu_buffers_in!="" && $seq_config!=""} {dc::set_max_delay -exception_name config_fu -from $seq_config -to $fu_buffers_in 3.0}
#for some (unknown) reason the DTL interface does not work if clock gated, clock gating
# is disabled for DTL interfaces within the CGRA
# OLD: set_attribute lp_clock_gating_exclude true */*CGRA_Compute_Wrapper*/*instances_hier*/*DTL*
set_attribute lp_clock_gating_exclude true [find . -instance */*CGRA_Compute_Wrapper*/*instances_hier*/*DTL*]
set_attribute lp_clock_gating_exclude true [find . -instance */*CGRA_Compute_Wrapper*/*instances_hier*/*LOADER*]
#set_attribute lp_clock_gating_exclude true [find . -instance */*CGRA_Compute_Wrapper*/*instances_hier*/*CGRA_Compute*/*instances_hier*/*lsu*]
set gm_out [find / -pin */CGRA_Top/GM_inst/genblk1.mem_inst/*]
#4.0
if {$fu_buffers_out!="" && $gm_out!=""} {dc::set_max_delay -exception_name fu_gm -from $fu_buffers_out -to $gm_out 2.8}
#if {$fu_buffers_out!=""} {dc::set_max_delay -exception_name fu_ff -from $fu_buffers_out -to $func_clk $FU_DELAY}
#reset input is asynchronous and therefore should be a false path
dc::set_false_path -from */$DESIGN/ports_in/$rst -exception_name reset
{
"folders" : {
"simulation" : "simulation",
"synthesis" : "synthesis",
"placeandroute" : "p+r",
"sources" : "source_code",
"root" : ""
},
"files" : {
"root" : [
"cds.lib"
],
"simulation" : [
"postpr.tcl",
"postsynthesis.tcl",
"Makefile",
"hdl.var",
"input.cmd"
],
"synthesis" : [
"Makefile",
"script/power.scr",
"script/power_pr.scr",
"script/tech_settings.scr",
"script/synth.scr",
"script/read_hdl.scr"
],
"placeandroute":[
"cpf/design.cpf",
"Makefile",
"p+r.tcl",
"script/design_import.tcl",
"script/analysis_settings.tcl",
"script/floorplan.tcl",
"script/floorplan_power.tcl",
"script/floorplan_macro.tcl",
"script/placement.tcl",
"script/cts.tcl",
"script/ctsSpec.ctstch",
"script/route.tcl",
"script/route_opt.tcl",
"script/post_route_opt.tcl",
"script/timing_derate.tcl",
"script/viewDefinition.tcl"
]
},
"simulation" : {
"tcf_scope" : "TB_CGRA_Top/dut/CGRA_Core_inst/CGRA_Compute_Wrapper_WR_inst/CGRA_Compute_Wrapper_inst"
},
"synthesis" : {
"clock_period" : "10000",
"clock_net" : "iClk",
"reset_net" : "iReset",
"driver_cell" : "DFQD1BWP12T40M1PLVT",
"disabled_cells" : ["EDF*", "SDF*", "DFC*", "DFS*", "DFD*", "DFN*", "DFK*", "DFS*", "DFX*"]
},
"power_est" : {
"clock_period" : "10000"
},
"placeandroute":{
"voltage" : "1.1",
"voltage_low" : "0.99",
"voltage_high" : "1.21",
"temperature" : "25",
"temperature_low" : "0",
"temperature_high" : "125",
"process" : "40",
"core_size" : "1.2 0.6",
"welltap_cell" : "TAPCELLBWP12T40M1P",
"clock_buffers" : ["CKBD0BWP12T40M1PLVT", "CKBD12BWP12T40M1PLVT", "CKBD16BWP12T40M1PLVT", "CKBD1BWP12T40M1PLVT", "CKBD20BWP12T40M1PLVT", "CKBD24BWP12T40M1PLVT", "CKBD2BWP12T40M1PLVT", "CKBD32BWP12T40M1PLVT", "CKBD3BWP12T40M1PLVT", "CKBD4BWP12T40M1PLVT", "CKBD6BWP12T40M1PLVT", "CKBD8BWP12T40M1PLVT"],
"antenna_cell" : "ANTENNABWP",
"filler_cells" : ["FILL64BWP", "FILL64BWPLVT", "FILL64BWPHVT", "FILL32BWP", "FILL32BWPLVT", "FILL32BWPHVT", "FILL16BWP", "FILL16BWPLVT", "FILL16BWPHVT", "FILL8BWP", "FILL8BWPLVT", "FILL8BWPHVT", "FILL4BWP", "FILL4BWPLVT", "FILL4BWPHVT", "FILL3BWP", "FILL3BWPLVT", "FILL3BWPHVT", "FILL2BWP", "FILL2BWPLVTvFILL2BWPHVT", "FILL1BWP", "FILL1BWPLVT", "FILL1BWPHVT"]
},
"source" : {
"data" : [
"out.bin",
"data.vbin"
],
"testbench" : {
"toplevel" : "TB_CGRA_Top",
"verilog" : [
"CGRA_core.v",
"CGRA_memory.v",
"CGRA_testbench.v",
"CGRA_top.v",
"DTL_Address_Isolator.v",
"DTL_ConsolePort.v",
"DTL_VGA.v",
"RAM_SDP.v",
"RAM_SDP_ALTERA.v",
"RAM_SDP_BE.v",
"STATE_CONTROLLER.v",
"DTL_SlaveInterface.v",
"DTL_Arbiter.v",
"DTL_MasterInterface.v",
"GM_Arbiter.v",
"GM_ARBITER_RR.v",
"ARBITER_RR.v",
"CGRA_WRAPPER.v"
],
"vhdl" : [
"dtl_sram_controller.vhd"
]
},
"synthesis" : {
"toplevel" : "CGRA_Compute_Wrapper",
"toplevel_file" : "CGRA_compute_wrapper.v",
"verilog" : [
"ABU.v",
"ARBITER_RR.v",
"DTL_SlaveInterface.v",
"ID.v",
"IU.v",
"LSU.v",
"ALU.v",
"CGRA_compute.v",
"DTL_Arbiter.v",
"DTL_MasterInterface.v",
"GM_Arbiter.v",
"GM_ARBITER_RR.v",
"IF.v",
"Loader.v",
"MUL.v",
"RF.v"
]
}
},
"libraries" : {
"operating_condition" : "/libraries/tcbn40lpbwp12t40m1plvtwc_ecsm/operating_conditions/WCCOM",
"io_lib" : "/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/IO2.5V/util/RC_QRC_cln40lp_1p08m+alrdl_5x2z",
"cds.lib" : "/home/eda/cadence/2014-15/RHELx86/INCISIVE_14.10.004/tools/inca/files/cds.lib",
"verilog" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/vlg/TSMCHOME/digital/Front_End/verilog/tcbn40lpbwp12t40m1plvt_200a/tcbn40lpbwp12t40m1plvt.v"
],
"lefs" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/sef/TSMCHOME/digital/Back_End/lef/tcbn40lpbwp12t40m1plvt_131a/lef/HVH_0d5_0/tcbn40lpbwp12t40m1plvt_8lm5X2ZRDL.lef"
],
"cap_tables_BC":[
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/sef/TSMCHOME/digital/Back_End/lef/tcbn40lpbwp12t40m1plvt_131a/techfiles/captable/cln40lp_1p08m+alrdl_5x2z_rcbest.captab"
],
"cap_tables_TC":[
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/sef/TSMCHOME/digital/Back_End/lef/tcbn40lpbwp12t40m1plvt_131a/techfiles/captable/cln40lp_1p08m+alrdl_5x2z_typical.captab"
],
"cap_tables_WC":[
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/sef/TSMCHOME/digital/Back_End/lef/tcbn40lpbwp12t40m1plvt_131a/techfiles/captable/cln40lp_1p08m+alrdl_5x2z_rcworst.captab"
],
"lib_name_BC" : "tcbn40lpbwp12t40m1plvtbc_ecsm",
"lib_name_TC" : "tcbn40lpbwp12t40m1plvttc_ecsm",
"lib_name_WC" : "tcbn40lpbwp12t40m1plvtwc_ecsm",
"libs_BC" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/ecsm/TSMCHOME/digital/Front_End/timing_power_noise/ECSM/tcbn40lpbwp12t40m1plvt_200a/tcbn40lpbwp12t40m1plvtbc_ecsm.lib"
],
"libs_TC" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/ecsm/TSMCHOME/digital/Front_End/timing_power_noise/ECSM/tcbn40lpbwp12t40m1plvt_200a/tcbn40lpbwp12t40m1plvttc_ecsm.lib"
],
"libs_WC" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/ecsm/TSMCHOME/digital/Front_End/timing_power_noise/ECSM/tcbn40lpbwp12t40m1plvt_200a/tcbn40lpbwp12t40m1plvtwc_ecsm.lib"
],
"cdb_BC" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/ctc/TSMCHOME/digital/Back_End/celtic/tcbn40lpbwp12t40m1plvt_200a/tcbn40lpbwp12t40m1plvtbc.cdb"
],
"cdb_TC" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/ctc/TSMCHOME/digital/Back_End/celtic/tcbn40lpbwp12t40m1plvt_200a/tcbn40lpbwp12t40m1plvttc.cdb"
],
"cdb_WC" : [
"/home/eda/Technology/TSMCHOME/40nm/Digital_200a/CMOS/LP/stclib/12-track/tcbn40lpbwp12t40m1p-set/tcbn40lpbwp12t40m1plvt_200a_FE/ctc/TSMCHOME/digital/Back_End/celtic/tcbn40lpbwp12t40m1plvt_200a/tcbn40lpbwp12t40m1plvtwc.cdb"
]
}
}
{
"folders" : {
"simulation" : "simulation",
"synthesis" : "synthesis",
"placeandroute" : "p+r",
"sources" : "source_code",
"root" : ""
},
"files" : {
"root" : [
"cds.lib"
],
"simulation" : [
"postpr.tcl",
"postsynthesis.tcl",
"Makefile",
"hdl.var",
"input.cmd"
],
"synthesis" : [
"Makefile",
"script/power.scr",
"script/power_pr.scr",
"script/tech_settings.scr",
"script/synth.scr",
"script/read_hdl.scr"
],
"placeandroute":[
"cpf/design.cpf",
"Makefile",
"p+r.tcl",
"script/design_import.tcl",
"script/analysis_settings.tcl",
"script/floorplan.tcl",
"script/floorplan_power.tcl",
"script/floorplan_macro.tcl",
"script/placement.tcl",
"script/cts.tcl",
"script/ctsSpec.ctstch",
"script/route.tcl",
"script/route_opt.tcl",
"script/post_route_opt.tcl",
"script/timing_derate.tcl",
"script/viewDefinition.tcl"
]
},
"simulation" : {
"tcf_scope" : "TB_CGRA_Top/dut/CGRA_Core_inst/CGRA_Compute_Wrapper_WR_inst/CGRA_Compute_Wrapper_inst"
},
"synthesis" : {
"clock_period" : "10000",
"clock_net" : "iClk",
"reset_net" : "iReset",
"driver_cell" : "DFQD1BWP12T40M1PLVT",
"disabled_cells" : ["EDF*", "SDF*", "DFC*", "DFS*", "DFD*", "DFN*", "DFK*", "DFS*", "DFX*"]
},
"power_est" : {
"clock_period" : "10000"
},
"placeandroute":{
"voltage" : "1.1",
"voltage_low" : "0.99",
"voltage_high" : "1.21",
"temperature" : "25",
"temperature_low" : "0",
"temperature_high" : "125",
"process" : "40",
"core_size" : "1.2 0.6",
"welltap_cell" : "TAPCELLBWP12T40M1P",
"clock_buffers" : ["CKBD0BWP12T40M1PLVT", "CKBD12BWP12T40M1PLVT", "CKBD16BWP12T40M1PLVT", "CKBD1BWP12T40M1PLVT", "CKBD20BWP12T40M1PLVT", "CKBD24BWP12T40M1PLVT", "CKBD2BWP12T40M1PLVT", "CKBD32BWP12T40M1PLVT", "CKBD3BWP12T40M1PLVT", "CKBD4BWP12T40M1PLVT", "CKBD6BWP12T40M1PLVT", "CKBD8BWP12T40M1PLVT"],
"antenna_cell" : "ANTENNABWP",
"filler_cells" : ["FILL64BWP", "FILL64BWPLVT", "FILL64BWPHVT", "FILL32BWP", "FILL32BWPLVT", "FILL32BWPHVT", "FILL16BWP", "FILL16BWPLVT", "FILL16BWPHVT", "FILL8BWP", "FILL8BWPLVT", "FILL8BWPHVT", "FILL4BWP", "FILL4BWPLVT", "FILL4BWPHVT", "FILL3BWP", "FILL3BWPLVT", "FILL3BWPHVT", "FILL2BWP", "FILL2BWPLVTvFILL2BWPHVT", "FILL1BWP", "FILL1BWPLVT", "FILL1BWPHVT"]
},
"source" : {
"data" : [
"out.bin",
"data.vbin"
],
"testbench" : {
"toplevel" : "TB_CGRA_Top",
"verilog" : [
"CGRA_core.v",
"CGRA_memory.v",
"CGRA_testbench.v",
"CGRA_top.v",
"DTL_Address_Isolator.v",
"DTL_ConsolePort.v",
"DTL_VGA.v",
"RAM_SDP.v",
"RAM_SDP_ALTERA.v",
"RAM_SDP_BE.v",
"RAM_SDP_BE_TSMC.v",
"RAM_SDP_TSMC.v",
"STATE_CONTROLLER.v",
"DTL_SlaveInterface.v",
"DTL_Arbiter.v",
"DTL_MasterInterface.v",
"General_Arbiter.v",
"ARBITER_GEN_RR.v",
"ARBITER_RR.v",
"CGRA_WRAPPER.v",
"ts6n40lpa256x12m4s_130a_tt1p1v25c.v",
"ts6n40lpa256x32m4s_130a_tt1p1v25c.v",
"ts6n40lpa256x33m2f_130a_tt1p1v25c.v"
],
"vhdl" : [
"dtl_sram_controller.vhd"
]
},
"testbench_synthesis" : {
"toplevel" : "TB_CGRA_Top",
"verilog" : [
"CGRA_core.v",
"CGRA_memory.v",
"CGRA_testbench.v",
"CGRA_top.v",
"DTL_Address_Isolator.v",
"DTL_ConsolePort.v",
"DTL_VGA.v",
"RAM_SDP.v",
"RAM_SDP_ALTERA.v",
"RAM_SDP_BE.v",
"RAM_SDP_BE_TSMC.v",
"RAM_SDP_TSMC.v",
"STATE_CONTROLLER.v",
"DTL_SlaveInterface.v",
"DTL_Arbiter.v",
"DTL_MasterInterface.v",
"General_Arbiter.v",
"ARBITER_GEN_RR.v",
"ARBITER_RR.v",
"CGRA_WRAPPER.v",
"ts6n40lpa256x12m4s_130a_tt1p1v25c.v",
"ts6n40lpa256x32m4s_130a_tt1p1v25c.v",
"ts6n40lpa256x33m2f_130a_tt1p1v25c.v"
],
"vhdl" : [
"dtl_sram_controller.vhd"
]
},
"synthesis" : {
"toplevel" : "CGRA_Compute_Wrapper",
"toplevel_file" : "CGRA_compute_wrapper.v",
"verilog" : [
<<SWITCHBOXES>>
"ABU.v",
"DATA_Buffer.v",
"Arbiter.v",
"ARBITER_RR.v",
"DTL_SlaveInterface.v",
"ID.v",
"IU.v",
"LSU.v",
"ALU.v",
"CGRA_compute.v",
"DTL_Arbiter.v",
"DTL_MasterInterface.v",
"General_Arbiter.v",
"ARBITER_GEN_RR.v",
"IF.v",
"Loader.v",
"MUL.v",
"RF.v",
"Address_Isolator.v"
]
}
},
"libraries" : {