Commit 90662f8e authored by E. Bruin de's avatar E. Bruin de
Browse files

- initial commit for eca 2020 course

parents
SHELL= /bin/sh
PLATFORM=convolution/naive
ROOT_DIR=../../..
MODELOPTS="-D 16"
# Note: DIALECT=1 overwrites existing PASM file.
DIALECT=0
include $(CGRA_ROOT)/tools/Makefiles/CGRA.mk
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# CREATOR: GIMP PNM Filter Version 1.1
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all:
@mkdir -p gen
gcc -o gen/lib_conv.so convolution.c -shared -fpic
python3 generate_reference.py
clean:
rm -rf gen
#define CHUNK_OFFSET 512
#define IMAGE_HEIGHT 100
#define IMAGE_WIDTH 100
#define CHUNK_HEIGHT 14 /* nice multiple of IMAGE_HEIGHT-2 */
#define CHUNK_WIDTH 14
void convolution_2d(unsigned char *input_samples, unsigned char *output_samples) {
static unsigned char iWeights[3][3] = {{1,2,1},{2,4,2},{1,2,1}};
static unsigned char chunk_samples[1024];
int x, y, tx, ty, kx, ky;
for (y=0; y < IMAGE_HEIGHT-2; y+=CHUNK_HEIGHT) {
for (x=0; x < IMAGE_WIDTH-2; x+=CHUNK_WIDTH) {
// DMA transfer (load new chunk)
for (ty=0; ty < CHUNK_HEIGHT+2; ty++) {
for (tx=0; tx < CHUNK_WIDTH+2; tx++) {
chunk_samples[ty*(CHUNK_WIDTH+2)+tx] = input_samples[(y+ty)*IMAGE_WIDTH+(x+tx)];
}
}
// Convolution (process chunk)
for (ty=0; ty < CHUNK_HEIGHT; ty++) {
for (tx=0; tx < CHUNK_WIDTH; tx++) {
// Kernel loop
int iSum = 0;
for (ky=0; ky < 3; ky++) {
for (kx=0; kx < 3; kx++) {
// printf("%i,%i,%i,%i,%i,%i: %i += %i * %i\n", y, x, ty, tx, ky, kx, iSum, chunk_samples[(ty+ky)*(CHUNK_WIDTH+2)+(tx+kx)], iWeights[ky][kx]);
iSum += chunk_samples[(ty+ky)*(CHUNK_WIDTH+2)+(tx+kx)] * iWeights[ky][kx];
}
}
// printf("%i,%i,%i,%i,%i,%i: %i += %i * %i\n", y, x, ty, tx, ky, kx, iSum, chunk_samples[(ty+ky)*(CHUNK_WIDTH+2)+(tx+kx)], iWeights[ky][kx]);
chunk_samples[CHUNK_OFFSET+ty*CHUNK_WIDTH+tx] = iSum >> 4;
}
}
// DMA transfer (store new chunk)
for (ty=0; ty < CHUNK_HEIGHT; ty++) {
for (tx=0; tx < CHUNK_WIDTH; tx++) {
output_samples[(y+ty)*(IMAGE_WIDTH-2)+(x+tx)] = chunk_samples[CHUNK_OFFSET+ty*CHUNK_WIDTH+tx];
}
}
}
}
}
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# created by the edge detect application
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\ No newline at end of file
#!/usr/bin/env python3
import os
import numpy as np
from os.path import join, dirname, realpath, exists
from helpers import convolution_2d, ImageConvertIn, ImageConvertOut, int2twosbin
script_dir = dirname(realpath(__file__))
if not exists(join(script_dir,'gen')):
os.makedirs(join(script_dir,'gen'))
# Generate data.vbin from image (.pgm) file
pgmInputFile = realpath(join(script_dir, '../naive/input_image.pgm'))
vbinFile = join(script_dir, 'gen/data.dma.vbin')
h,w,binaryData = ImageConvertIn(pgmInputFile, vbinFile)
# Load input data to 2d array and compute convolution
splitbytes = lambda ln: [int(ln[i:i+8],2) for i in range(0,len(ln),8)][::-1] # split and flip bytes
input_samples = np.array([splitbytes(ln) for ln in binaryData.splitlines()], dtype=np.uint8).reshape(h,w)
output_samples = convolution_2d(input_samples)
# Write expected output file (GM_out.txt)
MEM_SIZE = 8192 # 32kB
OUTPUT_OFFSET = 4096 # Write output at half of memory
gmFile = join(script_dir,'gen/GM_out.dma.txt')
with open(gmFile, 'w') as f:
#input samples
for i,(b1,b2,b3,b4) in enumerate(input_samples.reshape(-1,4)): # pack 4 8-bit values in single word
v = (b1 & 0xff) | ((b2 & 0xff) << 8) | ((b3 & 0xff) << 16) | ((b4 & 0xff) << 24)
f.write("{}\n".format(int2twosbin(v)))
#walk to OUTPUT_OFFSET
for i in range(i+1, OUTPUT_OFFSET):
f.write("{}\n".format('x'*32))
#output samples
for i,(b1,b2,b3,b4) in enumerate(output_samples.reshape(-1,4)): # pack 4 8-bit values in single word
v = (b1 & 0xff) | ((b2 & 0xff) << 8) | ((b3 & 0xff) << 16) | ((b4 & 0xff) << 24)
f.write("{}\n".format(int2twosbin(v)))
#walk to end of memory
for i in range(OUTPUT_OFFSET+i+1, MEM_SIZE):
f.write("{}\n".format('x'*32))
# Convert output file back to image
pgmOutputFile = join(script_dir,'gen/image_out.pgm')
ImageConvertOut(gmFile, OUTPUT_OFFSET, h-2, w-2, pgmOutputFile)
#!/usr/bin/env python3
import re
import textwrap
import numpy as np
import numpy.ctypeslib as npct
from os.path import join, dirname, realpath
script_dir = dirname(realpath(__file__))
# We wrap C functions from the shared library
libc = npct.load_library('gen/lib_conv.so', script_dir)
array_2d_uint8 = npct.ndpointer(dtype=np.uint8, ndim=2, flags='contiguous')
def convolution_2d(input_samples):
""" Desc: void convolution_2d(unsigned char *input_samples, unsigned char *output_samples); """
libc.convolution_2d.restype = None
libc.convolution_2d.argtypes = [array_2d_uint8, array_2d_uint8]
image_height, image_width = input_samples.shape
output_samples = np.zeros((image_height-2,image_width-2), dtype=np.uint8)
libc.convolution_2d(input_samples, output_samples)
return output_samples
def int2twosbin(number, bits=32):
""" Desc: integer to 2s complement binary """
bitstr = bin(number & int("1"*bits, 2))[2:] # do sign-extension
return ("{0:0>%s}" % (bits)).format(bitstr)
def bin2int(bitstr):
""" Desc: binary string to integer """
return int(bitstr,2)
def twosbin2int(bitstr):
""" Desc: 2s complement binary string to integer """
number = bin2int(bitstr)
return number if bitstr[0] == '0' else -((number ^ int("1"*len(bitstr),2)) + 1)
def int2hex(number, bits):
""" Return the 2s complement hexadecimal representation of an integer """
return hex((1 << bits) + number) if number < 0 else hex(number)
def ImageConvertIn(pgmFile, vbinFile):
inputData = open(pgmFile, 'r', encoding="ISO-8859-1").read()
wordSize = 4 # bytes per word
binaryData = ""
storeBinaryData = False
for line in inputData.split('\n'):
if storeBinaryData == True:
binaryData = binaryData + line
else:
m = re.match(r'\s*(\d+)\s+(\d+)', line) # retrieve dimensions
if m:
width,height = (int(v) for v in m.groups())
if line == "255": # maximum gray value
storeBinaryData = True
binaryList = list(binaryData)
binaryList += [chr(0)] * (wordSize - (len(binaryList) % wordSize))
binaryDataOut = [list(binaryList)[n:n+wordSize] for n in range(0, len(list(binaryList)), wordSize)]
binOut = ""
for word in binaryDataOut:
charList = [ord(i) for i in list(reversed(word))]
binWord = ""
for char in charList:
binWord += int2twosbin(char,8)
binOut += binWord + "\n"
open(vbinFile, 'w').write(binOut)
return height, width, binOut
def ImageConvertOut(gmFile, offset, height, width, pgmFile):
inputData = open(gmFile, 'r').read()
wordSize = 4 # bytes per word
scaleFactor = 1 # scale pixels by this factor
binOut = ""
for line in inputData.split('\n')[offset:offset+(width*height)//wordSize]:
for byte in list(reversed(textwrap.wrap(line, 8))):
if byte != "xxxxxxxx":
binOut += chr(int(byte,2)*(int(scaleFactor)))
else:
raise ValueError("Unexpected value '" + byte+ "' in output data")
binOut = "P5\n# created by the edge detect application\n" + str(width) + " " + str(height) + "\n255\n" + binOut
open(pgmFile, 'w', encoding="ISO-8859-1").write(binOut)
<?xml version="1.0" encoding="UTF-8"?>
<architecture>
<ISA>
<instructiontypes>
<T0>
<mnemonic type="mnemonic" width="7"></mnemonic>
<unused type="unused" width="5"></unused>
</T0>
<T1>
<mnemonic type="mnemonic" width="7"></mnemonic>
<registerX type="register" width="3"></registerX>
<inputA type="input" width="2"></inputA>
</T1>
<T2>
<mnemonic type="mnemonic" width="7"></mnemonic>
<registerX type="register" width="3"></registerX>
<unused type="unused" width="2"></unused>
</T2>
<T3>
<mnemonic type="mnemonic" width="7"></mnemonic>
<output type="output" width="1"></output>
<unused type="unused" width="2"></unused>
<inputA type="input" width="2"></inputA>
</T3>
<T4>
<mnemonic type="mnemonic" width="5"></mnemonic>
<datatype type="datatype" width="2"></datatype>
<unused type="unused" width="1"></unused>
<inputB type="input" width="2"></inputB>
<inputA type="input" width="2"></inputA>
</T4>
<T5>
<mnemonic type="mnemonic" width="5"></mnemonic>
<datatype type="datatype" width="2"></datatype>
<unused type="unused" width="3"></unused>
<inputA type="input" width="2"></inputA>
</T5>
<T6>
<mnemonic type="mnemonic" width="5"></mnemonic>
<datatype type="datatype" width="2"></datatype>
<output type="output" width="1"></output>
<inputB type="input" width="2"></inputB>
<unused type="unused" width="2"></unused>
</T6>
<T7>
<mnemonic type="mnemonic" width="5"></mnemonic>
<datatype type="datatype" width="2"></datatype>
<output type="output" width="1"></output>
<unused type="unused" width="4"></unused>
</T7>
<T8>
<mnemonic type="mnemonic" width="5"></mnemonic>
<datatype type="datatype" width="2"></datatype>
<output type="output" width="1"></output>
<inputB type="input" width="2"></inputB>
<inputA type="input" width="2"></inputA>
</T8>
<T9>
<mnemonic type="mnemonic" width="5"></mnemonic>
<datatype type="datatype" width="2"></datatype>
<output type="output" width="1"></output>
<unused type="unused" width="2"></unused>
<inputA type="input" width="2"></inputA>
</T9>
<T10>
<mnemonic type="mnemonic" width="7"></mnemonic>
<unused type="unused" width="1"></unused>
<inputB type="input" width="2"></inputB>
<inputA type="input" width="2"></inputA>
</T10>
<T11>
<mnemonic type="mnemonic" width="2"></mnemonic>
<registerY type="register" width="4"></registerY>
<registerX type="register" width="4"></registerX>
<inputA type="input" width="2"></inputA>
</T11>
<T12>
<mnemonic type="mnemonic" width="6"></mnemonic>
<registerX type="register" width="4"></registerX>
<inputA type="input" width="2"></inputA>
</T12>
<T13>
<mnemonic type="mnemonic" width="6"></mnemonic>
<registerX type="register" width="4"></registerX>
<unused type="unused" width="2"></unused>
</T13>
<T14>
<mnemonic type="mnemonic" width="7"></mnemonic>
<unused type="unused" width="1"></unused>
<inputB type="input" width="2"></inputB>
<unused0 type="unused" width="2"></unused0>
</T14>
<T15>
<mnemonic type="mnemonic" width="5"></mnemonic>
<output type="output" width="1"></output>
<immediate type="immediate" width="4"></immediate>
<unused type="unused" width="2"></unused>
</T15>
<T16>
<mnemonic type="mnemonic" width="7"></mnemonic>
<output type="output" width="1"></output>
<inputB type="input" width="2"></inputB>
<inputA type="input" width="2"></inputA>
</T16>
<T17>
<mnemonic type="mnemonic" width="5"></mnemonic>
<output type="output" width="1"></output>
<immediate type="immediate" width="4"></immediate>
<inputA type="input" width="2"></inputA>
</T17>
<T18>
<mnemonic type="mnemonic" width="4"></mnemonic>
<signtype type="signtype" width="3"></signtype>
<output type="output" width="1"></output>
<inputB type="input" width="2"></inputB>
<inputA type="input" width="2"></inputA>
</T18>
<T19>
<mnemonic type="mnemonic" width="4"></mnemonic>
<signtype type="signtype" width="3"></signtype>
<output type="output" width="1"></output>
<unused type="unused" width="2"></unused>
<inputA type="input" width="2"></inputA>
</T19>
<T20>
<mnemonic type="mnemonic" width="4"></mnemonic>
<immediate type="immediate" width="6"></immediate>
<unused type="unused" width="2"></unused>
</T20>
<T21>
<mnemonic type="mnemonic" width="4"></mnemonic>
<immediate type="immediate" width="6"></immediate>
<inputA type="input" width="2"></inputA>
</T21>
<T22>
<mnemonic type="mnemonic" width="7"></mnemonic>
<output type="output" width="1"></output>
<unused type="unused" width="4"></unused>
</T22>
<T23 width="32" hdl_param="I_IMM_WIDTH">
<mnemonic type="mnemonic" width="1"></mnemonic>
<unused type="unused" width="32"></unused>
</T23>
<T24 width="32" hdl_param="I_IMM_WIDTH">
<mnemonic type="mnemonic" width="1"></mnemonic>
<immediate type="immediate" width="32"></immediate>
</T24>
</instructiontypes>
<instructionFieldTypes>
<mnemonic width="7" separator="\s+"></mnemonic>
<unused width="1"></unused>
<register width="4" regex="r([0-3]?[0-9])" separator=","></register>
<input width="2" regex="in\[?([0-3])\]?" separator=","></input>
<output width="1" regex="out\[?([0-1])\]?" separator=","></output>
<immediate width="8" regex="([^\s,;\|]+)" separator=","></immediate>
<datatype width="2" regex="(([A-Z])+)" separator=","></datatype>
<signtype width="3" regex="(([A-Z])+)" separator=","></signtype>
</instructionFieldTypes>
<instructions>
<LSU>
<nop mnemonic="nop" type="T0" opcode="0"></nop>
<srm mnemonic="srm" type="T1" opcode="2"></srm>
<lrm mnemonic="lrm" type="T2" opcode="1"></lrm>
<pass mnemonic="pass" type="T3" opcode="8"></pass>
<sla mnemonic="sla" type="T4" opcode="8"></sla>
<sli mnemonic="sli" type="T5" opcode="9"></sli>
<lla mnemonic="lla" type="T6" opcode="10"></lla>
<lli mnemonic="lli" type="T7" opcode="11"></lli>
<lla_se mnemonic="lla_se" type="T6" opcode="12"></lla_se>
<lli_se mnemonic="lli_se" type="T7" opcode="13"></lli_se>
<lli_sla mnemonic="lli_sla" type="T8" opcode="14"></lli_sla>
<lla_sli mnemonic="lla_sli" type="T8" opcode="15"></lla_sli>
<lli_sli mnemonic="lli_sli" type="T9" opcode="4"></lli_sli>
<lli_se_sla mnemonic="lli_se_sla" type="T8" opcode="5"></lli_se_sla>
<lla_se_sli mnemonic="lla_se_sli" type="T8" opcode="6"></lla_se_sli>
<lli_se_sli mnemonic="lli_se_sli" type="T9" opcode="7"></lli_se_sli>
<dma_lga mnemonic="dma_lga" type="T10" opcode="9"></dma_lga>
<dma_sga mnemonic="dma_sga" type="T10" opcode="10"></dma_sga>
<dma_lga_2d mnemonic="dma_lga_2d" type="T10" opcode="11"></dma_lga_2d>
<dma_sga_2d mnemonic="dma_sga_2d" type="T10" opcode="4"></dma_sga_2d>
<dma_wait mnemonic="dma_wait" type="T0" opcode="5"></dma_wait>
</LSU>
<RF>
<nop mnemonic="nop" type="T0" opcode="0"></nop>
<lrm_srm mnemonic="lrm_srm" type="T11" opcode="1"></lrm_srm>
<srm mnemonic="srm" type="T12" opcode="2"></srm>
<lrm mnemonic="lrm" type="T13" opcode="3"></lrm>
<sra mnemonic="sra" type="T10" opcode="1"></sra>
<lra mnemonic="lra" type="T14" opcode="2"></lra>
</RF>
<ALU>
<nop mnemonic="nop" type="T0" opcode="0"></nop>
<lui mnemonic="lui" type="T15" opcode="8"></lui>
<add mnemonic="add" type="T16" opcode="4"></add>
<addi mnemonic="addi" type="T17" opcode="9"></addi>
<add_se mnemonic="add_se" type="T18" opcode="8"></add_se>
<sub mnemonic="sub" type="T16" opcode="28"></sub>
<subi mnemonic="subi" type="T17" opcode="10"></subi>
<sub_se mnemonic="sub_se" type="T18" opcode="11"></sub_se>
<and mnemonic="and" type="T16" opcode="1"></and>
<nand mnemonic="nand" type="T16" opcode="2"></nand>
<or mnemonic="or" type="T16" opcode="3"></or>
<nor mnemonic="nor" type="T16" opcode="24"></nor>
<xor mnemonic="xor" type="T16" opcode="25"></xor>
<xnor mnemonic="xnor" type="T16" opcode="18"></xnor>
<not mnemonic="not" type="T3" opcode="19"></not>
<cmov mnemonic="cmov" type="T16" opcode="30"></cmov>
<ecmov mnemonic="ecmov" type="T16" opcode="31"></ecmov>
<pass mnemonic="pass" type="T3" opcode="8"></pass>
<pass_se mnemonic="pass_se" type="T19" opcode="10"></pass_se>
<eq mnemonic="eq" type="T16" opcode="9"></eq>
<eqi mnemonic="eqi" type="T17" opcode="11"></eqi>
<neq mnemonic="neq" type="T16" opcode="10"></neq>
<ltu mnemonic="ltu" type="T16" opcode="11"></ltu>
<lts mnemonic="lts" type="T16" opcode="12"></lts>
<geu mnemonic="geu" type="T16" opcode="13"></geu>
<ges mnemonic="ges" type="T16" opcode="14"></ges>
<shll1 mnemonic="shll1" type="T3" opcode="15"></shll1>
<shll4 mnemonic="shll4" type="T3" opcode="5"></shll4>
<shrl1 mnemonic="shrl1" type="T3" opcode="6"></shrl1>
<shrl4 mnemonic="shrl4" type="T3" opcode="7"></shrl4>
<shra1 mnemonic="shra1" type="T3" opcode="16"></shra1>
<shra4 mnemonic="shra4" type="T3" opcode="17"></shra4>
</ALU>
<ABU>
<nop mnemonic="nop" type="T0" opcode="0"></nop>
<srm mnemonic="srm" type="T12" opcode="7"></srm>
<lrm mnemonic="lrm" type="T13" opcode="4"></lrm>
<jr mnemonic="jr" type="T14" opcode="1"></jr>
<ja mnemonic="ja" type="T14" opcode="4"></ja>
<bcr mnemonic="bcr" type="T10" opcode="5"></bcr>
<bca mnemonic="bca" type="T10" opcode="2"></bca>
<accu mnemonic="accu" type="T12" opcode="5"></accu>
<accs mnemonic="accs" type="T12" opcode="6"></accs>
<jri mnemonic="jri" type="T20" opcode="5"></jri>
<jai mnemonic="jai" type="T20" opcode="4"></jai>
<bcri mnemonic="bcri" type="T21" opcode="6"></bcri>
<bcai mnemonic="bcai" type="T21" opcode="7"></bcai>
</ABU>
<MUL>
<nop mnemonic="nop" type="T0" opcode="0"></nop>
<lh mnemonic="lh" type="T22" opcode="1"></lh>
<pass mnemonic="pass" type="T3" opcode="8"></pass>
<shra8 mnemonic="shra8" type="T3" opcode="9"></shra8>
<shra16 mnemonic="shra16" type="T3" opcode="10"></shra16>
<shra24 mnemonic="shra24" type="T3" opcode="11"></shra24>
<mullu mnemonic="mullu" type="T16" opcode="12"></mullu>
<mullu_sh8 mnemonic="mullu_sh8" type="T16" opcode="13"></mullu_sh8>
<mullu_sh16 mnemonic="mullu_sh16" type="T16" opcode="14"></mullu_sh16>
<mullu_sh24 mnemonic="mullu_sh24" type="T16" opcode="15"></mullu_sh24>
<mulls mnemonic="mulls" type="T16" opcode="16"></mulls>
<mulls_sh8 mnemonic="mulls_sh8" type="T16" opcode="17"></mulls_sh8>
<mulls_sh16 mnemonic="mulls_sh16" type="T16" opcode="18"></mulls_sh16>
<mulls_sh24 mnemonic="mulls_sh24" type="T16" opcode="19"></mulls_sh24>
<mulu mnemonic="mulu" type="T16" opcode="4"></mulu>
<mulu_sh8 mnemonic="mulu_sh8" type="T16" opcode="5"></mulu_sh8>
<mulu_sh16 mnemonic="mulu_sh16" type="T16" opcode="22"></mulu_sh16>
<mulu_sh24 mnemonic="mulu_sh24" type="T16" opcode="23"></mulu_sh24>
<muls mnemonic="muls" type="T16" opcode="2"></muls>
<muls_sh8 mnemonic="muls_sh8" type="T16" opcode="3"></muls_sh8>
<muls_sh16 mnemonic="muls_sh16" type="T16" opcode="20"></muls_sh16>
<muls_sh24 mnemonic="muls_sh24" type="T16" opcode="21"></muls_sh24>
</MUL>
<IU>
<nopi mnemonic="nopi" type="T23" opcode="0"></nopi>
<imm mnemonic="imm" type="T24" opcode="1"></imm>
</IU>
</instructions>
</ISA>
<DataTypes>
<byte width="8"></byte>
<hword width="16"></hword>
<word width="32"></word>
<dword width="64"></dword>
</DataTypes>
<PeripheralTypes>
<Console addr_range="1">
<Toplevel_connections>
<connection name="WriteData" type="output" width="32"></connection>
<connection name="WriteValid" type="output" width="1"></connection>
<connection name="WriteEnable" type="output" width="4"></connection>
</Toplevel_connections>
</Console>
<VGA addr_range="1048576">
<Toplevel_connections>
<connection name="VGAClk" type="input" width="1"></connection>
<connection name="VGA_R" type="output" width="8"></connection>
<connection name="VGA_G" type="output" width="8"></connection>
<connection name="VGA_B" type="output" width="8"></connection>
<connection name="VGA_Clk" type="output" width="1"></connection>
<connection name="VGA_Sync" type="output" width="1"></connection>
<connection name="VGA_Blank" type="output" width="1"></connection>
<connection name="VGA_VS" type="output" width="1"></connection>
<connection name="VGA_HS" type="output" width="1"></connection>
</Toplevel_connections>
</VGA>
<FIFO addr_range="10">
<Toplevel_connections></Toplevel_connections>
</FIFO>
</PeripheralTypes>
<Core>
<StateSwitch enabled="0"></StateSwitch>
<ZeroOverheadLoops enabled="0"></ZeroOverheadLoops>
<PerformanceCounters enabled="1"></PerformanceCounters>
<Branchslots slots="2"></Branchslots>
<DecodedInstructions width="16"></DecodedInstructions>
<DataPath width="32" hdl_param="D_WIDTH"></DataPath>
<Loader offset="1C110000"></Loader>
<Memory type="SCM_LATCH">
<GM width="32" depth="4096" addresswidth="32" interface="DTL"></GM>
<LM width="32" depth="256" addresswidth="16"></LM>
<IM depth="256" addresswidth="16"></IM>
<SM width="32" depth="256" addresswidth="32"></SM>
</Memory>
<Interface width="32" addresswidth="32" max_blockwidth="5"></Interface>
</Core>
<configuration>
<functionalunittypes>
<ID>
<reconfiguration bits="3"></reconfiguration>
<connections inputs="1" outputs="0"></connections>
</ID>
<IU>
<reconfiguration bits="0"></reconfiguration>
<connections inputs="1" outputs="1"></connections>
</IU>
<LSU>
<control idtype="0"></control>
<reconfiguration bits="0"></reconfiguration>
<connections inputs="4" outputs="2"></connections>
</LSU>
<RF>
<control idtype="1"></control>
<reconfiguration bits="0"></reconfiguration>
<connections inputs="4" outputs="2"></connections>
</RF>
<ALU>
<control idtype="2"></control>
<reconfiguration bits="1"></reconfiguration>
<connections inputs="4" outputs="2"></connections>
</ALU>
<ABU>
<control idtype="3"></control>
<reconfiguration bits="1"></reconfiguration>
<connections inputs="4" outputs="2"></connections>
</ABU>